IBM unveils world's first sub-1nm chip tech for data centers
What's the story
IBM has unveiled a groundbreaking new chip architecture that can pack nearly 100 billion transistors into a chip the size of a human fingernail. This is almost double the transistor density of its previous generation of chip technology. The revolutionary development, which IBM calls the "world's first sub-1 nanometer (nm) chip technology," is aimed at artificial intelligence (AI) data centers and promises significant improvements in computing performance and energy efficiency.
Technological advancement
Meaningful leap forward
Jay Gambetta, Director of IBM Research and an IBM Fellow, described the new chip technology as a "meaningful leap forward." He said it points to a future where computing can be much more powerful without consuming more energy. The term "sub-1nm chip technology" refers to the performance gains that would be seen if a theoretical chip could be made with features smaller than 1nm.
Innovative design
Nanostack architecture overcomes scaling limits
IBM's new "nanostack" architecture overcomes the scaling limits of modern chip designers by vertically stacking transistors in a staggered layout. This allows more transistors to be packed into the same chip space. The basic unit of this architecture is two bonded and stacked transistors, each made up of three nanosheets that are 5nm thick, equivalent to about 15 rows of silicon atoms.
Performance boost
Projected improvements
The nanostack architecture could offer 50% more computing power or 70% greater energy efficiency than IBM's previous generation of 2nm node chips. This is according to projections from the company's technical reports. In addition, IBM researchers have demonstrated that the nanostack architecture can deliver a 40% improvement in scaling for static random-access memory (SRAM), which is critical for many AI applications.
Memory improvement
SRAM scaling
The memory improvement with the nanostack architecture comes from a staggered-channel design for the chip's SRAM bit cells. This reduces the overall cell height by 40% and allows more SRAM to be packed into the same chip space. The development is likely to be welcomed by chip designers looking to support AI workloads, given how SRAM scaling has drastically fallen in recent generations of chip technologies.
Commercialization prospects
Commercialization and future prospects
IBM has partnered with semiconductor companies such as Rapidus in Japan to mass manufacture its previous generation of 2nm node chips. However, it hasn't revealed specific companies it may partner with for commercializing the latest sub-1nm node technology. Huiming Bu, VP of IBM Semiconductors Global R&D and IBM Research, expects that commercial chips made at this new node could start production within five years and become mainstream within a decade.