Vidyavardhaka College of Engineering (VVCE) in Mysuru just wrapped up its PINAKA Academic Tapeout project, marking a big leap for Indian semiconductor research.
The team designed a chip using RISC-V architecture and 65-nanometer tech, all based on indigenous RISC-V architecture and developed using 65-nanometre technology.
The milestone, completed on November 13, brought together members of the college management, representatives of AstraSemi and KYROS SEMI, principal and vice-principal of VVCE, Head of the Department of Electronics and Communication Engineering, and the principal investigator and co-principal investigator of the project.
VVCE PINAKA gives students hands-on experience
PINAKA is a joint effort with AstraSemi and KYROS SEMI that gives students hands-on experience with real-world chip design. The finished chip has now been sent to TSMC in Taiwan for tapeout.
VVCE Principal Sadashive Gowda said the PINAKA initiative marked a milestone for the institution, demonstrating the potential of academic research and industry collaboration in semiconductor innovation, while inspiring students and faculty to contribute to India's growing indigenous chip design ecosystem.