IIT Guwahati researchers' breakthrough improves lifetime of NVM cache memory
Researchers at the Indian Institute of Technology, Guwahati (IIT-G) have made a breakthrough in memory architectures used by non-volatile memory (NVM) of computers. The researchers' methodology helps prevent data redundancy while improving slow, frequent data writes that plague systems using multi-core processors. Specifically, the solution helps processors that need large caches to keep up with the demands of applications without running too hot.
Lead researcher Dr. Hemangee K Kapoor from the Department of Computer Science Engineering at IIT-G explained that applications don't program the data access patterns to use caches uniformly. This causes some memory locations to be written and read more often than others, causing undue wear and increasing chances of data redundancy. It also prevents usage of the entire NVM without error correction.
To handle this non-uniformity, the researchers developed methods to evenly distribute the accesses across the overall cache memory capacity to reduce the pressure on the heavily written parts that are prone to wearing out.
This avoids writing redundant values repeatedly (which slows down the process) and increases the service life of the processor's NVM cache by prolonging the wear-out process.
The first two methods explored by the researchers partition the cache into windows of equal size and distribute the writes equally across the cache set by preventing writes where desired using the read-only access protocol. The windows are selected by rotation or using a counter. In the third technique, researchers used different write-restricted cache ways to distribute the writes uniformly.
The new breakthrough is also poised to help the on-chip memory meet the demand of applications while preventing additional energy consumption. This ensures the temperatures of the processor stay under the designed thermal limits known as thermal design power (TDP) limit measured in watts. Since energy consumption is proportional to the energy wastage in the form of heat.
The researchers claim that the experimental results obtained after performing a full system simulation showed a significant reduction in intra-set write variation and an improvement in the lifetime of the NVM cache. Additionally, the researchers explained that the slow and frequent writes can be redirected to temporary SRAM partitions sparing the NVM from getting worn out due to frequent accesses.
The team is also working on extending the slow frequent writes to off-chip main memory. The upcoming challenges in this area of research are to handle lifetime enhancement in the presence of encryption methods used to secure non-volatile memory. Another challenge ahead is to handle temperature and process technology-driven disturbance errors that are introduced when the cells are read or written.
This research is being led by IIT Bombay alumnus and Vice-President of the ACM India Council, Dr. Kapoor, and research scholar Sukarn Agarwal. The other contributing research scholars are Palash Das, Sheel Sindhu Manohar, Arijit Nath, and Khushboo Rani. Their research paper authored by Dr. Kapoor and Agarwal has been published in the IEEE Transactions on Computers journal.